The present invention relates generally to phase lock loops and, more particularly, to a digital phase lock loop employing a programmable delay line to minimize phase error of a clock signal with respect to a reference signal.
Present day data recording systems record data in digital form, typically employing a coding format such as modified-frequency modulation (MFM). The data on the recording media is broken into sectors which contain synchronization fields and data fields. Each of the fields is broken up into bit cells which are precisely defined. The bits of data are coded by defining the order and positions of magnetic flux reversals or transitions within each bit cell. Thus, it is extremely important to very accurately determine the position of the flux transitions within a bit cell to be able to decode the data. The bit cell is defined by a data clock. It is necessary that the data clock be synchronized, or locked, to the data in order to define a data "window" at the proper time to correctly decode the data. A bit cell will contain one, or more, data windows; the number of data windows in a bit cell is a function of the data coding method used.
Typically, a tape or disc drive controller will include a data separator or similar circuitry, whose function is to recover the data from the coded data stream. The data separator circuitry will comprise several functional blocks including an analog phase lock loop (consisting of a phase comparator, voltage controlled oscillator (VCO), error amplifier, low pass filter and pulse synchronizing logic) to lock the data clock to the data. Analog phase lock loops are prone to locking to harmonics and are also vulnerable to noise and data drop out.
One commercially available product (designated UPD9306 Hard Disc Interface manufactured by NEC Electronics Inc.) simulates the function of an analog VCO by utilizing two delay lines. One of the external delay lines is used to generate ten equally phase-shifted reference clocks, each clock having a frequency of 10 MHz. The total delay line delay is 100 nanoseconds (ns), which is equal to the clock period. A phase comparator utilizes the second delay line to divide a bit cell into ten separate intervals. The VCO signal is synthesized by selecting one of the phase-shifted clock signals. The clock signal selected depends on where the sampling edge of the data clock falls within the bit cell. The rate at which the clock is phase-shifted in one direction or the other corresponds to an increase or decrease in resultant frequency.